The subject matter disclosed herein relates to circuit card assemblies, and more particularly, to three-dimensional microcircuit card assemblies including passive thermal transfer interfaces.
The demand for reduced chip packaging has led to increased functional convergence as well as increased packaging complexity and sophistication. These demands have led to a shift in chip packaging technology from two-dimensional (2D) packaging to more advanced “two and a half dimensional” or pseudo three-dimensional (2.5D), and three-dimensional (3D) package designs.
Traditional 2D packaging involves chip design layouts that are arranged across a single plane, typically referred to as the horizontal plane, or along the length and width of a substrate. Traditional 2.5D designs were developed to incorporate multiple chips in a single package by arranging the chips in a planar fashion around an interposer. The interposer gradually could then be replaced by through-silicon vias as chips are thinned out and bonded together. The 3D packaging approach is typically viewed as arranging chips not only along the horizontal plane (i.e., the length of width of a substrate), but also along the vertical plane (e.g., height) by stacking chips atop one another. This stacked arrangement provided by 3D packaging requires improved thermal management, which is typically addressed using active heating devices such as fans or fluid-based heat exchangers.